[PATCH] D99057: [TableGen] Allow BitsInit to init integer in pseudo expansion
Serge Pavlov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 22 09:12:52 PDT 2021
sepavloff updated this revision to Diff 332319.
sepavloff added a comment.
Addressed reviewer's notes
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D99057/new/
https://reviews.llvm.org/D99057
Files:
llvm/test/TableGen/pseudo-inst-expansion.td
llvm/utils/TableGen/PseudoLoweringEmitter.cpp
Index: llvm/utils/TableGen/PseudoLoweringEmitter.cpp
===================================================================
--- llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -108,6 +108,12 @@
OperandMap[BaseIdx + i].Kind = OpData::Imm;
OperandMap[BaseIdx + i].Data.Imm = II->getValue();
++OpsAdded;
+ } else if (auto *BI = dyn_cast<BitsInit>(Dag->getArg(i))) {
+ auto II = dyn_cast<IntInit>(BI->convertInitializerTo(IntRecTy::get()));
+ assert(II && "Cannot convert to integer initializer");
+ OperandMap[BaseIdx + i].Kind = OpData::Imm;
+ OperandMap[BaseIdx + i].Data.Imm = II->getValue();
+ ++OpsAdded;
} else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
// Just add the operands recursively. This is almost certainly
// a constant value for a complex operand (> 1 MI operand).
Index: llvm/test/TableGen/pseudo-inst-expansion.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/pseudo-inst-expansion.td
@@ -0,0 +1,37 @@
+// RUN: llvm-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def TestTargetInstrInfo : InstrInfo;
+
+def TestTarget : Target {
+ let InstructionSet = TestTargetInstrInfo;
+}
+
+def REG : Register<"REG">;
+def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
+
+class SysReg<bits<12> op> {
+ bits<12> Encoding = op;
+}
+def SR : SysReg<0b111100001111>;
+
+class Pseudo<dag outs, dag ins, list<dag> pattern>
+ : Instruction {
+ dag OutOperandList = outs;
+ dag InOperandList = ins;
+ let Pattern = pattern;
+ let isPseudo = 1;
+}
+
+def INSTR : Instruction {
+ let OutOperandList = (outs GPR:$rd);
+ let InOperandList = (ins i32imm:$val);
+ let Pattern = [];
+}
+
+def PSEUDO : Pseudo<(outs GPR:$rd), (ins),
+ [(set GPR:$rd, (i32 SR.Encoding))]>,
+ PseudoInstExpansion<(INSTR GPR:$rd, SR.Encoding)>;
+
+// CHECK: .addOperand(MCOperand::createImm(3855));
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