[PATCH] D99026: [RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64

Jessica Clarke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Mar 20 12:45:50 PDT 2021

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jrtc27 added a comment.

I think the final line of your commit message is the wrong way round?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99026/new/

https://reviews.llvm.org/D99026

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