[PATCH] D98821: [RISCV] Improve 64-bit integer materialization for some cases.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/sadd_sat.ll:109
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    slli a2, a2, 63
+; RV64I-NEXT:    j .LBB1_3
----------------
This is a regression, but was suboptimal before. We have a select_cc picking between INT64_MIN and INT64_MAX. Those are only one apart with wraparound. We could just generate one constant and add/sub the result of a sltz to it to generate the other constant.

I think DAG combine would normally do that for select of constants, but the select here is created during LegalizeDAG and is turned into select_cc immediately so DAG combine never sees it.


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Comment at: llvm/test/CodeGen/RISCV/sadd_sat.ll:153
 ; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    addi a0, a0, -1
+; RV64IZbb-NEXT:    slli a2, a2, 63
+; RV64IZbb-NEXT:    j .LBB1_3
----------------
Same here


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Comment at: llvm/test/CodeGen/RISCV/sadd_sat_plus.ll:116
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    slli a1, a1, 63
+; RV64I-NEXT:    j .LBB1_3
----------------
And here


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Comment at: llvm/test/CodeGen/RISCV/sadd_sat_plus.ll:160
 ; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    addi a0, a0, -1
+; RV64IZbb-NEXT:    slli a1, a1, 63
+; RV64IZbb-NEXT:    j .LBB1_3
----------------
And here


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98821/new/

https://reviews.llvm.org/D98821