[PATCH] D98802: [RISCV][WIP] Fix offset computation for RVV

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

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In D97111 <https://reviews.llvm.org/D97111> we changed the RVV frame layout so addressing emergency spill slots was not impossible when there are RVV stack slots.

To do so we need to skip the "scalar" part (that we put in lower offsets from the reference register `sp` / `fp`). The size of the scalar part is computed subtracting the callee saved register size (whose computation is added in D97111 <https://reviews.llvm.org/D97111> itself) to the total size of the stack (which does not account for RVV stack slots). However, we round to 16 bytes when computing that size and we end emitting a smaller offset that may belong to a scalar stack slot.

My understanding is that we do not have to round the size of the callee saved registers and instead we need to round up the offset iself obtained from having skipped the scalar part. This should work because VLENB is a power of two larger or equal than 128. The stack is already correctly aligned to 16 bytes when we grow it for the RVV stack slots.

I think the alignment constraint holds for RV32 as well.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98802

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot.mir

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