[PATCH] D98249: [SVE] Suppress vselect warning from incorrect interface call
Nashe Mncube via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 17 03:32:15 PDT 2021
nasherm updated this revision to Diff 331204.
nasherm added a comment.
Slight change to the checking call which triggers the warning. We now
check using the ElementCount interface.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98249/new/
https://reviews.llvm.org/D98249
Files:
llvm/include/llvm/CodeGen/ValueTypes.h
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-vselect-interface-warnings.ll
Index: llvm/test/CodeGen/AArch64/sve-vselect-interface-warnings.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-vselect-interface-warnings.ll
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple=aarch64-linux-unknown -mattr=+sve -o - < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix="WARN" --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+define <vscale x 8 x i8> @vselect_cmp_ne(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c) {
+ ; CHECK-LABEL: vselect_cmp_ne
+ ; CHECK: // %bb.0
+ ; CHECK-NEXT: mov z3.d, z1.d
+ ; CHECK-NEXT: and z3.h, z3.h, #0xff
+ ; CHECK-NEXT: and z0.h, z0.h, #0xff
+ ; CHECK-NEXT: ptrue p0.h
+ ; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z3.h
+ ; CHECK-NEXT: sel z0.h, p0, z1.h, z2.h
+ ; CHECK-NEXT: ret
+ %cmp = icmp ne <vscale x 8 x i8> %a, %b
+ %d = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c
+ ret <vscale x 8 x i8> %d
+}
+
+define <vscale x 8 x i8> @vselect_cmp_sgt(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c) {
+ ; CHECK-LABEL: vselect_cmp_sgt
+ ; CHECK: // %bb.0
+ ; CHECK-NEXT: ptrue p0.h
+ ; CHECK-NEXT: sxtb z3.h, p0/m, z1.h
+ ; CHECK-NEXT: sxtb z0.h, p0/m, z0.h
+ ; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z3.h
+ ; CHECK-NEXT: sel z0.h, p0, z1.h, z2.h
+ ; CHECK-NEXT: ret
+ %cmp = icmp sgt <vscale x 8 x i8> %a, %b
+ %d = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c
+ ret <vscale x 8 x i8> %d
+}
+
+define <vscale x 8 x i8> @vselect_cmp_ugt(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c) {
+ ; CHECK-LABEL: vselect_cmp_ugt
+ ; CHECK: // %bb.0
+ ; CHECK-NEXT: mov z3.d, z1.d
+ ; CHECK-NEXT: and z3.h, z3.h, #0xff
+ ; CHECK-NEXT: and z0.h, z0.h, #0xff
+ ; CHECK-NEXT: ptrue p0.h
+ ; CHECK-NEXT: cmphi p0.h, p0/z, z0.h, z3.h
+ ; CHECK-NEXT: sel z0.h, p0, z1.h, z2.h
+ ; CHECK-NEXT: ret
+ %cmp = icmp ugt <vscale x 8 x i8> %a, %b
+ %d = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c
+ ret <vscale x 8 x i8> %d
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15139,7 +15139,8 @@
}
}
- if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
+ if (N0.getOpcode() != ISD::SETCC ||
+ CCVT.getVectorElementCount() != ElementCount::getFixed(1) ||
CCVT.getVectorElementType() != MVT::i1)
return SDValue();
Index: llvm/include/llvm/CodeGen/ValueTypes.h
===================================================================
--- llvm/include/llvm/CodeGen/ValueTypes.h
+++ llvm/include/llvm/CodeGen/ValueTypes.h
@@ -298,6 +298,7 @@
}
/// Given a vector type, return the number of elements it contains.
+ /// This assumes a fixed-vector type.
unsigned getVectorNumElements() const {
#ifdef STRICT_FIXED_SIZE_VECTORS
assert(isFixedLengthVector() && "Invalid vector type!");
@@ -323,7 +324,8 @@
return getExtendedVectorElementCount();
}
- /// Given a vector type, return the minimum number of elements it contains.
+ /// Given a (possibly scalable) vector type, return the minimum number of
+ /// elements it contains.
unsigned getVectorMinNumElements() const {
return getVectorElementCount().getKnownMinValue();
}
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