[PATCH] D94964: [LangRef] Describe memory layout for vectors types

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/docs/LangRef.rst:3214
+A bitcast from a vector type to a scalar integer type will see the elements
+being packed toghether (without padding). The order in which elements are
+inserted in the integer depends on endianess. For little endian element zero
----------------
together 


================
Comment at: llvm/docs/LangRef.rst:3226
+
+When ``<N*M>`` isn't evenly divisible by the byte size the memory layout is
+unspecified.
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Does this apply to a v4i1? I thought that worked the same way as any other i1 type. The defined bits end up in the MSBs.


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