[PATCH] D98549: [AMDGPU] Fix copyPhysReg to not produce unalined vgpr access

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:915-918
+  } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && !RI.hasAGPRs(SrcRC) &&
+             (RC == RI.getVGPRClassForBitWidth(Size) &&
+              (RI.isSGPRClass(SrcRC) ||
+               SrcRC == RI.getVGPRClassForBitWidth(Size)))) {
----------------
rampitec wrote:
> rampitec wrote:
> > arsenm wrote:
> > > This seems more complicated than it needs to be
> > Suggestions?
> I.e. I do not see an easy way to check an RC is aligned.
Probably should add a utility function to check this. The verifier has a similarly confusing check here:

```
    if (!RC || ((IsVGPR && !RC->hasSuperClassEq(RI.getVGPRClassForBitWidth(
                                 RI.getRegSizeInBits(*RC)))) ||

```


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  https://reviews.llvm.org/D98549/new/

https://reviews.llvm.org/D98549