[PATCH] D98501: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

I can see that the shift amount should be XLen, but is there a crash that this fixes? Or is it that it shouldn't be possible to generate these intrinsics in the first place? I'm wondering what (if anything) can be put in place to stop this from happening again.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D98501