[PATCH] D98501: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

[Zakk Chen via Phabricator via llvm-commits]

khchen created this revision.
khchen added reviewers: craig.topper, frasercrmck.
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Fix the unexpected of using op1's element type as shift amount type.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98501

Files:
  llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll