[PATCH] D98356: [MCA] Support in-order CPUs with MicroOpBufferSize=1

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

In D98356#2617708 <https://reviews.llvm.org/D98356#2617708>, @foad wrote:

>> is this patch needed because otherwise you see the following crash/assertion failure?
>
> Yes, that was the failure, and I just did the minimum work I could to make MicroOpBufferSize=1 work like MicroOpBufferSize=0. I don't really know what reorder buffers and retire control units are -- they are not part of my mental model of how the AMDGPU processors work.

Fair enough :).
Your patch looks good. Thanks!


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