[PATCH] D98250: [RISCV] Optimize INSERT_VECTOR_ELT sequences

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2267
+    ValInVec = DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, I32ContainerVT, ValInVec,
+                           ValLo, I32Mask, InsertI64VL);
+  }
----------------
frasercrmck wrote:
> craig.topper wrote:
> > Don't we need a bitcast here to get back to the ContainerVT to match the SDTypeProfile for the next operation?
> Good catch, thanks. I've fixed that up.
> 
> On a related note, I noticed that it was perfectly content when using the original container mask, even though `SDTCisSameNumEltsAs` shouldn't have let (e.g.) nxv2i1 match against nxv4i1. The code for the TableGen constraint seems like it should be working, so maybe it's something in our patterns? I didn't have time to dig in more deeply.
The SDTypeProfiles cause tablegen to remove type checks from the isel table to minimize table size assuming the rules have been followed.. So if you tell it that something has the same number of elements as another result or operand and tell it the specific element type it won't emit a check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98250/new/

https://reviews.llvm.org/D98250