[PATCH] D95677: [AArch64][SVE] Add unpredicated ld1/st1 patterns for reg+reg addressing modes

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll:142-157
+define void @ld1b_reg([64 x i8]* %addr, i64 %off) {
+; CHECK-LABEL: ld1b_reg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cntw x8
+; CHECK-NEXT:    add x8, x1, x8
+; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0, x8]
----------------
These tests look more complex than necessary for the ISel patterns they're exercising.  Is something akin to the following not sufficient?
```
define <vscale x 16 x i8> @ld1b_reg(i8* %base, i64 %off) {
 %ptr = getelementptr inbounds i8, i8*%base, i64 %off
 %ptrcast = bitcast i8* %ptr to <vscale x 16 x i8>*
 %val = load <vscale x 16 x i8>, <vscale x 16 x i8>* %ptrcast
 ret %val
```





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Comment at: llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll:169
+
+define void @st1b_reg([64 x i8]* %addr, i64 %off, <vscale x 16 x i8> %val) {
+; CHECK-LABEL: st1b_reg:
----------------
Same comment as for the loads.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95677/new/

https://reviews.llvm.org/D95677