[PATCH] D98310: [RISCV] WIP Support extract_vector_elt for fixed masked registers.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Does this need to be limited to fixed-length vectors? We're currently unable to do this on scalable vectors too.

As you say, I suspect for vectors of (vscale x) 8/16/32/64/etc x i1 we 'd be better bitcasting to i8, extract an element and shift down any remaining bits. Not sure what's best for 2/4. Insert into a larger vector and do the same process? Same problem as for subvectors, really. A set of mask-vector slide instructions would be great.


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