[PATCH] D97480: [RISCV] Support inline asm for vector instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:8087
+  MVT RegVT = *TRI.legalclasstypes_begin(*RC);
+  if (RegVT.getSizeInBits() != RefOpInfo.ConstraintVT.getSizeInBits()) {
+    auto E = TRI.legalclasstypes_end(*RC);
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frasercrmck wrote:
> Does this case trigger for any other target?
> 
> I'm curious: what made you choose this method in the end?
I prefer to use target hooks to solve the issue.
I think I misunderstood you. I will revert it back.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97480/new/

https://reviews.llvm.org/D97480