[PATCH] D94816: [P10] [Power PC] Exploiting new load rightmost vector element instructions.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:3972
+// Any big endian Power9 VSX subtarget
+let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in {
+// Power10 VSX subtargets produce a shorter pattern for little endian targets
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The patterns appear to be the same. Why do we split this out into LE/BE if the patterns are endianness neutral? If they are the same, merge them into a single block that doesn't have an endianness predicate.


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  https://reviews.llvm.org/D94816/new/

https://reviews.llvm.org/D94816