[PATCH] D98236: [RISCV] Add SiFive-VIU75 for llvm

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 requested changes to this revision.
jrtc27 added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:281-283
+                                                    FeatureStdExtV,
+                                                    FeatureStdExtZvlsseg,
+                                                    FeatureExtZvamo,
----------------
I don't think we should ever enable V and related extensions here for two reasons:

1. They're currently experimental, so -mcpu=sifive-viu75 bypasses -menable-experimental-extensions.

2. They're still drafts that are going to see changes and we don't maintain backwards compatibility between draft revisions, so as soon as there's a new draft spec we'll have to remove these extensions from this model as the core will no longer implement the spec version we do.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98236/new/

https://reviews.llvm.org/D98236