[PATCH] D98236: [RISCV] Add SiFive-VIU75 for llvm

[ShihPo Hung via Phabricator via llvm-commits]

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This patch adds support for the SiFive CPU VIU75.

details of the CPU can be found here:
https://www.sifive.com/cores/viu75


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98236

Files:
  llvm/lib/Target/RISCV/RISCV.td


Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -272,6 +272,17 @@
                                                   FeatureStdExtD,
                                                   FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-viu75", SiFive7Model, [Feature64Bit,
+                                                    FeatureStdExtM,
+                                                    FeatureStdExtA,
+                                                    FeatureStdExtF,
+                                                    FeatureStdExtD,
+                                                    FeatureStdExtC,
+                                                    FeatureStdExtV,
+                                                    FeatureStdExtZvlsseg,
+                                                    FeatureExtZvamo,
+                                                    FeatureExtZfh]>;
+
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//


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