[PATCH] D98102: [RISCV] Add support for fixed vector reductions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

In D98102#2611638 <https://reviews.llvm.org/D98102#2611638>, @craig.topper wrote:

> Only 3 targets use the VECREDUCE nodes today, AArch64, ARM, and RISCV. X86 does not use them yet. AArch64 doesn't have this problem because their largest integer type is their largest vector element type. ARM doesn't appear to support i64 reductions.

Ah right okay, thanks. Anyway, the changes LGTM. I don't know if the size of the test files is a problem. It's not unprecedented but it still makes me uncomfortable.


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  https://reviews.llvm.org/D98102/new/

https://reviews.llvm.org/D98102