[PATCH] D98102: [RISCV] Add support for fixed vector reductions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D98102#2610721 <https://reviews.llvm.org/D98102#2610721>, @frasercrmck wrote:

> Wow yeah that's some heavy scalarization. I think I came across some situations where custom vector legalization may be required, as you say. It just felt odd, though. Do any other targets have to do this, other than simple hi/lo splitting?

Only 3 targets use the VECREDUCE nodes today, AArch64, ARM, and RISCV. X86 does not use them yet. AArch64 doesn't have this problem because their largest integer type is their largest vector element type. ARM doesn't appear to support i64 reductions.


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