[PATCH] D98174: [MCA] Add tests for IPC on Cortex-A55

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added inline comments.


================
Comment at: llvm/test/tools/llvm-mca/AArch64/Cortex/IPC/A55-4.s:6-7
+# FIXME: DIV is not modeled precisely: on hardware it takes variable
+# number of cycles depending on its operands. LLVM scheduling model
+# only provides an average latency.
+#
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RKSimon wrote:
> dmgreen wrote:
> > andreadb wrote:
> > > Not sure if it might help in this case, but in general I recommend to have a look at whether some operand constraints might be defined using MCSchedPredicate defs in SchedWriteVariant.
> > Is this something that is fixable in llvm? I thought it would not, in general, know the input value for an instruction.
> You might be able to do something with valuetracking - if you know the upper bits are zero/signsplat etc. But I don't think we have any knownbits/signbits support this late on in the compile.
Yeah, I don’t think that there is anything that we can do about that specifically.


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https://reviews.llvm.org/D98174