[PATCH] D98033: [AArch64][SVEIntrinsicOpts] Factor out redundant SVE mul/fmul intrinsics

[Joe Ellis via Phabricator via llvm-commits]

joechrisellis created this revision.
joechrisellis added reviewers: david-arm, paulwalker-arm, peterwaller-arm.
Herald added subscribers: hiraditya, kristof.beyls, tschuett.
joechrisellis requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This commit implements an IR-level optimization to eliminate idempotent
SVE mul/fmul intrinsic calls. Currently, the following patterns are
captured:

  fmul  pg  (dup_x  1.0)  V  =>  V
  mul   pg  (dup_x  1)    V  =>  V
  
  fmul  pg  V  (dup_x  1.0)  =>  V
  mul   pg  V  (dup_x  1)    =>  V
  
  fmul  pg  V  (dup  v  pg  1.0)  =>  V
  mul   pg  V  (dup  v  pg  1)    =>  V

The result of this commit is that code such as:

  1  #include <arm_sve.h>
  2
  3  svfloat64_t foo(svfloat64_t a) {
  4    svbool_t t = svptrue_b64();
  5    svfloat64_t b = svdup_f64(1.0);
  6    return svmul_m(t, a, b);
  7  }

will lower to a nop.

This commit does not capture all possibilities; only the simple cases
described above. There is still room for further optimisation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98033

Files:
  llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
  llvm/test/CodeGen/AArch64/sve-fmul-idempotency.ll
  llvm/test/CodeGen/AArch64/sve-mul-idempotency.ll

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