[PATCH] D96351: [PowerPC][AIX] Enable the default AltiVec ABI on AIX

[Zarko Todorovski via Phabricator via llvm-commits]

ZarkoCA added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:446
   case PPC::VFRCRegClassID:
-  case PPC::VSLRCRegClassID:
+  case PPC::VSLRCRegClassID: {
+    const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
----------------
sfertile wrote:
> With this change we will need to split up these cases.
> 
> The pre VSX register sets are the easiest to explain:
> 
> `F8RC` --> This is the F0-F31, which represents the 32 fprs with type f64.
> `F4RC` --> This is the same as F8RC but with type f32.
> 
> These register sets won't change in the default ABI and will still have 32 available registers.
> 
> `VRRC` --> This is V0-V31 and represents the vector registers. With the extended ABI we can access all of them, with the default ABI we have the limited set of the first 20.
> 
> Once we add VSX it gets complicated: the other register sets are how we represent the registers with VSX. VSX has 64 128-bit wide registers. The fprs are mapped into element 0 of the first 32 VSX registers (VSR0-VSR31), with the vrs are mapped into the the second set of 32 VSX registers (VSR32-VSR64).
> 
> `VFRC` --> This is the set of 32 64-bit floating point sub registers not overlapped by the fprs (vsr32-vsr64). Used in instructions like lxsd/stxsd where we encode a register number N between 0-31 in the instruction but the instruction targets the sub register 32 + N.
> 
> `VSLRC` --> The 32 128-bit registers that the fprs overlap (vs0-vsr31).
> 
> `VSRC` -->  `VSLRC U VR` vsr0-vsr31 + vsr31-vsr63 = vsr0-vsr63, or all the vsx vector registers.
> `VSFRC` --> `VFRC U F8RC` all the 64-bit sub registers of the vsx vector registers.
> `VSSRC` --> Same as VSFRC but the with type f32.
> 
> The qvecnvol option doesn't mention vsx registers but I would assume any that overlap the VRs are affected the same way, and the scalar registers which overlap vsr0-vsr31 are unaffectedly by the option. I'm not sure if there is any restriction on the vector registers vsr0-vsr31 in the default ABI.
> 
Thanks for this detailed explanation.  
I updated the switch cases to reflect my understanding of this.  

```
case PPC::VRRCRegClassID: {
    const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
    if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
      return 20 - DefaultSafety;
  }
    LLVM_FALLTHROUGH;

```
The above seems straightforward to me but I can also change the fallthrough if it's not preferred.

I am less certain about this:

```
  case PPC::VSRCRegClassID: {
    const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
    if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
      return 64 - 12 - DefaultSafety;
  }
    return 64 - DefaultSafety;
```
In the default ABI, VSX registers vsr54-63 should map to default abi registers v20-v31 and be reserved, and it's what I get from looking at `PPCRegisterInfo.td`.

```
343 def VRRC : RegisterClass<"PPC",
344                          [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128],
345                          128,
346                          (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
347                              V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
348                              V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
...
355 def VSRC  : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
356                           (add VSLRC, VRRC)>;
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D96351/new/

https://reviews.llvm.org/D96351