[PATCH] D97812: [mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero

[Daniel Sanders via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9fc2be6f289e: [mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero (authored by dsanders).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97812/new/

https://reviews.llvm.org/D97812

Files:
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
  llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
  llvm/test/CodeGen/MIR/AArch64/base-memoperands.mir
  llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
  llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
  llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
  llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir
  llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp