[PATCH] D97729: [ARM] Improve WLS lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 328115.
dmgreen added a comment.

Thanks for taking a look. I'm not sure this is best to split out into a separate review though. Just as in D89881 <https://reviews.llvm.org/D89881>, it makes sense to keep the langref and the codegen changes together, as an atomic commit. Because the intinsics is specified as:

  def int_test_start_loop_iterations :
    DefaultAttrsIntrinsic<[llvm_anyint_ty, llvm_i1_ty], [LLVMMatchType<0>], [IntrNoDuplicate]>;

.. It should be correct by construction, with the types matching between into and output. I don't think there's much to verify really, as these intrinsics are only generated by the hardware loop pass and consumed by ISel. As the reference says,

  These intrinsics may be modified in the future and are not intended to be used
  outside the backend. Thus, front-end and mid-level optimizations should not be
  generating these intrinsics.

I've tried to add some extra details, like the other intrinsics.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97729/new/

https://reviews.llvm.org/D97729

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/HardwareLoops.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMBlockPlacement.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
  llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
  llvm/lib/Target/ARM/MVETailPredUtils.h
  llvm/lib/Target/ARM/MVETailPredication.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
  llvm/test/CodeGen/Thumb2/block-placement.mir
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll
  llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll
  llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll
  llvm/test/Transforms/HardwareLoops/ARM/structure.ll
  llvm/test/Transforms/HardwareLoops/loop-guards.ll
  llvm/test/Transforms/HardwareLoops/scalar-while.ll

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