[PATCH] D97549: [RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 4 01:32:29 PST 2021
frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.
LGTM. I wouldn't say my last suggestion is a hard requirement.
================
Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll:1
+; RUN: opt < %s -loop-vectorize -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -S | FileCheck %s
+
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We could perhaps add an extra RUN line for riscv32 just to make sure nothing silly is going on.
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https://reviews.llvm.org/D97549/new/
https://reviews.llvm.org/D97549
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