[PATCH] D97549: [RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector

[Luke via Phabricator via llvm-commits]

luke957 added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll:1
+; RUN: opt < %s -loop-vectorize -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-max=128 -riscv-v-vector-bits-min=128 -S | FileCheck %s
+
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HsiangKai wrote:
> `-mattr=+experimental-v` should be enough.
> 
> Should we specify `-riscv-v-vector-bits-max` in this test case?
Yeah, "-riscv-v-vector-bits-max" is not needed.


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  https://reviews.llvm.org/D97549/new/

https://reviews.llvm.org/D97549