[PATCH] D97884: [dfsan] Remove hard-coded shadow width in more tests

[stephan.yichao.zhao via Phabricator via llvm-commits]

stephan.yichao.zhao added inline comments.


================
Comment at: llvm/test/Instrumentation/DataFlowSanitizer/external_mask.ll:10
 ; CHECK: and {{.*}}%[[RV:.*]]
-; CHECK: mul i64
   %1 = load i32, i32* %b, align 4
----------------
gbalats wrote:
> stephan.yichao.zhao wrote:
> > Is this one testing 2x for 16bit mode? This is still useful to lock down generated IR.
> > 
> > 
> Exactly. That instruction won't be generated with 8bit mode, which is why I removed it so that the test can work in both modes in the future. If we want to keep it, do you have any suggestions on how to make it conditional (only when SBYTES != 1)?
Some test cases also check the pattern of loading an i32 value like
```
x = load
y = load
z = or x y
```
The two modes have different numbers of these loads and ors. That also requires two check prefixes.


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  https://reviews.llvm.org/D97884/new/

https://reviews.llvm.org/D97884