[PATCH] D97604: [SystemZ] Reimplement the 1-byte compare-and-swap logic
Jonas Paulsson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 3 10:36:31 PST 2021
jonpa added a comment.
> This is not needed any more -- it is already done by common code now that you set getAtomicExtendOps to ZERO_EXTEND.
I also thought so, but I found that it did make a difference on this test case: F15722631: boolean_cmpxchg.uint8.ll <https://reviews.llvm.org/F15722631>
Not sure exactly why, but thought we might as well have it there... Or is this a bug in common code we should fix?
Or is it perhaps even good without the AssertZext - the differnece in this case is an LLGFR instead of LLGCR. I thought maybe that could make a difference in other programs...
Before isel:
Optimized legalized selection DAG: %bb.0 '_Z3funh:entry' Optimized legalized selection DAG: %bb.0 '_Z3funh:entry'
SelectionDAG has 28 nodes: | SelectionDAG has 27 nodes:
t0: ch = EntryToken t0: ch = EntryToken
t19: ch = lifetime.end<0 to 1> t45:2, TargetFrameIndex:i64<0> t19: ch = lifetime.end<0 to 1> t45:2, TargetFrameIndex:i64<0>
t34: i64 = any_extend t45 | t49: i32 = AssertZext t45, ValueType:ch:i8
t36: i64 = and t34, Constant:i64<255> | t59: i64 = zero_extend t49
t22: ch,glue = CopyToReg t19, Register:i64 $r2d, t36 | t22: ch,glue = CopyToReg t19, Register:i64 $r2d, t59
t11: ch = lifetime.start<0 to 1> t0, TargetFrameIndex:i64<0> t11: ch = lifetime.start<0 to 1> t0, TargetFrameIndex:i64<0>
t30: ch = store<(store 1 into %ir.0, align 2), trunc to i8> t11, C t30: ch = store<(store 1 into %ir.0, align 2), trunc to i8> t11, C
t39: i64 = and FrameIndex:i64<0>, Constant:i64<-4> t39: i64 = and FrameIndex:i64<0>, Constant:i64<-4>
t2: i64,ch = CopyFromReg t0, Register:i64 %0 t2: i64,ch = CopyFromReg t0, Register:i64 %0
t24: i64 = AssertZext t2, ValueType:ch:i8 t24: i64 = AssertZext t2, ValueType:ch:i8
t29: i32 = truncate t24 t29: i32 = truncate t24
t43: i32 = sub Constant:i32<0>, t57 | t43: i32 = sub Constant:i32<0>, t58
t45: i32,i32,ch = SystemZISD::ATOMIC_CMP_SWAPW<(volatile load store | t45: i32,i32,ch = SystemZISD::ATOMIC_CMP_SWAPW<(volatile load store
t56: i32 = truncate FrameIndex:i64<0> | t57: i32 = truncate FrameIndex:i64<0>
t57: i32 = shl t56, Constant:i32<3> | t58: i32 = shl t57, Constant:i32<3>
t23: ch = SystemZISD::RET_FLAG t22, Register:i64 $r2d, t22:1 t23: ch = SystemZISD::RET_FLAG t22, Register:i64 $r2d, t22:1
output
.text .text
.file "boolean_cmpxchg.cpp" .file "boolean_cmpxchg.cpp"
.globl _Z3funh # -- Begin function _Z .globl _Z3funh # -- Begin function _Z
.p2align 4 .p2align 4
.type _Z3funh, at function .type _Z3funh, at function
_Z3funh: # @_Z3funh _Z3funh: # @_Z3funh
.cfi_startproc .cfi_startproc
# %bb.0: # %entry # %bb.0: # %entry
stmg %r13, %r15, 104(%r15) stmg %r13, %r15, 104(%r15)
.cfi_offset %r13, -56 .cfi_offset %r13, -56
.cfi_offset %r14, -48 .cfi_offset %r14, -48
.cfi_offset %r15, -40 .cfi_offset %r15, -40
aghi %r15, -168 aghi %r15, -168
.cfi_def_cfa_offset 328 .cfi_def_cfa_offset 328
la %r3, 166(%r15) la %r3, 166(%r15)
mvi 166(%r15), 1 mvi 166(%r15), 1
risbgn %r1, %r3, 0, 189, 0 risbgn %r1, %r3, 0, 189, 0
l %r5, 0(%r1) l %r5, 0(%r1)
sll %r3, 3 sll %r3, 3
lcr %r4, %r3 lcr %r4, %r3
lhi %r0, 0 lhi %r0, 0
.LBB0_1: # %entry .LBB0_1: # %entry
# =>This Inner Loop Header: De # =>This Inner Loop Header: De
rll %r14, %r5, 8(%r3) rll %r14, %r5, 8(%r3)
risbg %r0, %r14, 32, 55, 0 risbg %r0, %r14, 32, 55, 0
llcr %r14, %r14 llcr %r14, %r14
crjlh %r14, %r2, .LBB0_3 crjlh %r14, %r2, .LBB0_3
# %bb.2: # %entry # %bb.2: # %entry
# in Loop: Header=BB0_1 Dept # in Loop: Header=BB0_1 Dept
rll %r13, %r0, -8(%r4) rll %r13, %r0, -8(%r4)
cs %r5, %r13, 0(%r1) cs %r5, %r13, 0(%r1)
jl .LBB0_1 jl .LBB0_1
.LBB0_3: # %entry .LBB0_3: # %entry
llgcr %r2, %r14 | llgfr %r2, %r14
lmg %r13, %r15, 272(%r15) lmg %r13, %r15, 272(%r15)
br %r14 br %r14
.Lfunc_end0: .Lfunc_end0:
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D97604/new/
https://reviews.llvm.org/D97604
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