[PATCH] D97698: [RISCV] Support fixed-length INSERT_VECTOR_ELT

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked 2 inline comments as done.
frasercrmck added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll:13
+; RV32-NEXT:    vle64.v v26, (a0)
+; RV32-NEXT:    vsetvli a3, zero, e64,m2,ta,mu
+; RV32-NEXT:    vmv.v.x v28, a2
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craig.topper wrote:
> Should this also be 4 instead of VLMAX?
This one's not fixed by D97842, but that might be a better place to discuss why?


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll:137
+; RV32-NEXT:    vslidedown.vx v8, v28, a2
+; RV32-NEXT:    vsetvli a4, zero, e16,m4,ta,mu
+; RV32-NEXT:    vmv.s.x v8, a1
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craig.topper wrote:
> Looking at this again, should this be using 32 instead of VLMAX?
Yes, sorry about that oversight. D97842 fixes it.


Repository:
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  https://reviews.llvm.org/D97698/new/

https://reviews.llvm.org/D97698