[PATCH] D97698: [RISCV] Support fixed-length INSERT_VECTOR_ELT

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll:137
+; RV32-NEXT:    vslidedown.vx v8, v28, a2
+; RV32-NEXT:    vsetvli a4, zero, e16,m4,ta,mu
+; RV32-NEXT:    vmv.s.x v8, a1
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Looking at this again, should this be using 32 instead of VLMAX?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97698/new/

https://reviews.llvm.org/D97698