[PATCH] D97762: [RISCV] fixes cross unwinding failure

[Saleem Abdulrasool via Phabricator via llvm-commits]

compnerd accepted this revision.
compnerd added a comment.
This revision is now accepted and ready to land.

Ah right, the !RISCV -> RISCV case.  This makes sense to commit to fix the immediate issue.

Thinking about this more, ILP32 is not permitted on RISC-V 64 and ILP-64 is not permitted on RISC-V 32 (which for some reason I had backwards).  I think that it would make sense to avoid using RISC-V macros entirely and use `__SIZEOF_POINTER__` to select the register width (`__SIZEOF_POINTER__ == 8` would mean that we should use `uint64_t` and a value of `4` would indicate `uint32_t`).  Furthermore, we could then replace the use of `__riscv_flen` with `__SIZEOF_DOUBLE__` to select between `float` and `double` for the `fpret_t` rather than the `__riscv_flen`.  That would completely alleviate having to have 4 different configurations to worry about - {native, x-unwind} * {defined, undefined}.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97762/new/

https://reviews.llvm.org/D97762