[PATCH] D97274: [RISCV] replace unuseful emergency spill slot test with a mir test

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Isn't this very similar to https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir except for a missing `SD`?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97274/new/

https://reviews.llvm.org/D97274