[PATCH] D97111: [RISCV] change rvv frame layout

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Can we add some tests for the cases with overaligned stuff and variable sized + rvv?

Something like this (feel free to improve if needed)

  define void @rvv_vla(i64 %n, i64 %i) nounwind {
    %vla.addr = alloca i32, i64 %n
  
    %v1.addr = alloca <vscale x 1 x i64>
    %v1 = load volatile <vscale x 1 x i64>, <vscale x 1 x i64>* %v1.addr
  
    %v2.addr = alloca <vscale x 2 x i64>
    %v2 = load volatile <vscale x 2 x i64>, <vscale x 2 x i64>* %v2.addr
  
    %p = getelementptr i32, i32* %vla.addr, i64 %i
    %s = load volatile i32, i32* %p
    ret void
  }
  
  define void @rvv_overaligned(i64 %n, i64 %i) nounwind {
    %overaligned = alloca i32, align 64
  
    %v1.addr = alloca <vscale x 1 x i64>
    %v1 = load volatile <vscale x 1 x i64>, <vscale x 1 x i64>* %v1.addr
  
    %v2.addr = alloca <vscale x 2 x i64>
    %v2 = load volatile <vscale x 2 x i64>, <vscale x 2 x i64>* %v2.addr
  
    %s = load volatile i32, i32* %overaligned, align 64
    ret void
  }

and a combined version of both.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97111/new/

https://reviews.llvm.org/D97111