[PATCH] D97634: [DAGCombiner] Optimize 1-bit smulo to AND+SETNE.
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 28 10:27:17 PST 2021
RKSimon added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4669
+ DAG.getSetCC(DL, CarryVT, And,
+ DAG.getConstant(0, DL, VT), ISD::SETNE));
+ }
----------------
Why not just handle the simplification of SMULO/UMULO of i1/vXi1 in getNode() ? I doubt any hardware has actual instructions for bool types so will expand to icmp/logic ops whatever.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D97634/new/
https://reviews.llvm.org/D97634
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