[PATCH] D88389: [M68k] (Patch 3/8) Basic infrastructures and target description files

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/M68k/M68kCallingConv.td:18
+class CCIfSubtarget<string F, CCAction A>
+    : CCIf<!strconcat("static_cast<const M68kSubtarget&>"
+                       "(State.getMachineFunction().getSubtarget()).", F), A>;
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jrtc27 wrote:
> (yes, there are places in LLVM that get this wrong if you go looking)
Not done


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Comment at: llvm/lib/Target/M68k/M68kInstrFormats.td:180
+/// If the EA is a direct register mode, bits 4 and 5 are 0, and the register
+/// number will be encoded in bit 0 - 3. Since the first register's
+/// (A0) register number is 8, we can easily tell data registers from
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I do think this needs to say _address_ register; the first register is D0 with encoding 0, no?


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Comment at: llvm/lib/Target/M68k/M68kInstrShiftRotate.td:67
+
+def NAME#"8dd"  : MxSR_DD<MN, MxType8d,  NODE, RODI, ROOP>;
+def NAME#"16dd" : MxSR_DD<MN, MxType16d, NODE, RODI, ROOP>;
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You missed this multiclass


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88389/new/

https://reviews.llvm.org/D88389