[PATCH] D97480: [RISCV] Support inline asm for vector instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6218
+      // PartVT first.
+      if (ValueEltVT != PartEltVT) {
+        unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
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frasercrmck wrote:
> In what situations are the element types not equal? Does the PartVT come from the first type in the RC?
Yes, the PartVT comes from the first type in the RC. Another way to handle it is to search the corresponding type in the RC in GetRegistersForValue(). The problem comes from we reuse VR register class for fractional LMUL types.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6219
+      if (ValueEltVT != PartEltVT) {
+        unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
+        EVT SameEltTypeVT = EVT::getVectorVT(Context, PartEltVT, Count, true);
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frasercrmck wrote:
> Is this guaranteed not to become 0?
Yes, I reordered the supported types in VR. The first type has the element type i8. In addition, I created VM register class for mask register types.


Repository:
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  https://reviews.llvm.org/D97480/new/

https://reviews.llvm.org/D97480