[PATCH] D97480: [RISCV] Support inline asm for vector instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6218
+      // PartVT first.
+      if (ValueEltVT != PartEltVT) {
+        unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
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In what situations are the element types not equal? Does the PartVT come from the first type in the RC?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6219
+      if (ValueEltVT != PartEltVT) {
+        unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
+        EVT SameEltTypeVT = EVT::getVectorVT(Context, PartEltVT, Count, true);
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Is this guaranteed not to become 0?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6220
+        unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
+        EVT SameEltTypeVT = EVT::getVectorVT(Context, PartEltVT, Count, true);
+        Val = DAG.getNode(ISD::BITCAST, DL, SameEltTypeVT, Val);
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Maybe put a `/*IsScalable*/` on the `true`?


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Comment at: llvm/test/CodeGen/RISCV/rvv/inline-asm.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -o - < %s \
+; RUN:     --verify-machineinstrs | FileCheck %s
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Nit, but `-o -` and `< %s` isn't too common a combination: `< %s` or `-o - %s`?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97480/new/

https://reviews.llvm.org/D97480