[PATCH] D97480: [RISCV] Support inline asm for vector instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 326427.
HsiangKai added a comment.

Convert V0~V31 to the super register if the value type is belong to M2 <https://reviews.llvm.org/M2>/M4/M8.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97480/new/

https://reviews.llvm.org/D97480

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

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