[PATCH] D97480: [RISCV] Support inline asm for vector instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

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Types of fractional LMUL and LMUL=1 are all using VR register class. When
using inline asm, it will use the first type in the register class as the
type for the register. It is not necessary the same as the value type. We
need to use INSERT_SUBVECTOR/EXTRACT_SUBVECToR/BITCAST to make it legal
to put the value in the corresponding register class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97480

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

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