[PATCH] D94395: [X86] AMD Znver3 Scheduler descriptions and llvm-mca tests

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:1170
+
+// VPERM2F128.
+def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>;
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Matt wrote:
> I'm wondering, would you happen to know whether there's a chance that marking `VPERM2F128` as "Microcoded Instruction" (with Latency = 100) is a leftover from a previous Zen microarchitecture scheduler?
> 
> It seems this is no longer the case for Zen 3; cf. https://www.agner.org/optimize/instruction_tables.pdf reporting macro-operations=1, latency=3.5, and reciprocal throughput=0.5 for the `y,y,y/m,i` instruction variant.
Yes, there are a lot of numbers in this patch that look like a direct copy+paste from the znver2 model (which was mainly a copy+paste of the znver1 model), and all of them diverge from what Agner, instlatx64 and the AMD SoG tables all report. For this patch to get any further we need llvm-exegesis to be run on the model to determine how accurate it really is. Otherwise we're better off just staying with the existing zen models.


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  https://reviews.llvm.org/D94395/new/

https://reviews.llvm.org/D94395