[PATCH] D94395: [X86] AMD Znver3 Scheduler descriptions and llvm-mca tests

[Matt D. via Phabricator via llvm-commits]

Matt added inline comments.


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Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:1170
+
+// VPERM2F128.
+def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>;
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I'm wondering, would you happen to know whether there's a chance that marking `VPERM2F128` as "Microcoded Instruction" (with Latency = 100) is a leftover from a previous Zen microarchitecture scheduler?

It seems this is no longer the case for Zen 3; cf. https://www.agner.org/optimize/instruction_tables.pdf reporting macro-operations=1, latency=3.5, and reciprocal throughput=0.5 for the `y,y,y/m,i` instruction variant.


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  https://reviews.llvm.org/D94395/new/

https://reviews.llvm.org/D94395