[PATCH] D96980: [amdgpu] Revert agnostic SGPR spill.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D96980#2587642 <https://reviews.llvm.org/D96980#2587642>, @ruiling wrote:

>>> (I get the argument that IR does not run code if exec = 0, however, MIR models the hardware rather than a high-level language, and exec = 0 is perfectly fine there and even required in some cases, like for the last null export inserted in SIInsertSkips.)
>>
>> I'm not convinced this always works. It's possible some transformation ends up violating this. We need to track both sets of predecessors and add some verification for this
>
> What do you mean by "violating this"? Do you mean some transformation may failed to keep a jump on EXEC = 0 for each divergent branching?

Yes. The MIR doesn't track divergent predecessors and we don't have any verification for this


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96980/new/

https://reviews.llvm.org/D96980