[PATCH] D97218: [AMDGPU] Set threshold for regbanks reassign pass

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 325539.
rampitec added a comment.

Fixed debug output.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97218/new/

https://reviews.llvm.org/D97218

Files:
  llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp


Index: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
+++ llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
@@ -48,6 +48,11 @@
   cl::value_desc("0|1|2"),
   cl::init(0), cl::Hidden);
 
+// Threshold to keep compile time reasonable.
+static cl::opt<unsigned> VRegThresh("amdgpu-regbanks-reassign-threshold",
+  cl::desc("Max number of vregs to run the regbanks reassign pass"),
+  cl::init(100000), cl::Hidden);
+
 #define DEBUG_TYPE "amdgpu-regbanks-reassign"
 
 #define NUM_VGPR_BANKS 4
@@ -807,6 +812,16 @@
     return false;
 
   MRI = &MF.getRegInfo();
+
+  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
+                    << "\nNumVirtRegs = " << MRI->getNumVirtRegs() << "\n\n");
+
+  if (MRI->getNumVirtRegs() > VRegThresh) {
+    LLVM_DEBUG(dbgs() << "NumVirtRegs > " << VRegThresh
+                      << " threshold, skipping function.\n\n");
+    return false;
+  }
+
   TRI = ST->getRegisterInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
   VRM = &getAnalysis<VirtRegMap>();
@@ -826,9 +841,6 @@
                          AMDGPU::SReg_32RegClass.getNumRegs() / 2 + 1;
   RegsUsed.resize(NumRegBanks);
 
-  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
-               << '\n');
-
   unsigned StallCycles = collectCandidates(MF);
   NumStallsDetected += StallCycles;
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D97218.325539.patch
Type: text/x-patch
Size: 1474 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210222/04656af0/attachment-0001.bin>