[PATCH] D97218: [AMDGPU] Set threshold for regbanks reassign pass

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: alex-t, foad.
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This is to limit compile time. I did experiments with some
inputs and found that compile time keeps reasonable for this
pass if we have less than 100000 virtual registers and then
starts to explode somewhere between 100000 and 150000.


https://reviews.llvm.org/D97218

Files:
  llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp


Index: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
+++ llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
@@ -48,6 +48,11 @@
   cl::value_desc("0|1|2"),
   cl::init(0), cl::Hidden);
 
+// Threshold to keep compile time reasonable.
+static cl::opt<unsigned> VRegThresh("amdgpu-regbanks-reassign-threshold",
+  cl::desc("Max number of vregs to run the regbanks reassign pass"),
+  cl::init(100000), cl::Hidden);
+
 #define DEBUG_TYPE "amdgpu-regbanks-reassign"
 
 #define NUM_VGPR_BANKS 4
@@ -807,6 +812,16 @@
     return false;
 
   MRI = &MF.getRegInfo();
+
+  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
+                    << "\nNumVirtRegs = " << MRI->getNumVirtRegs() << "\n\n");
+
+  if (MRI->getNumVirtRegs() > VRegThresh) {
+    LLVM_DEBUG(dbgs() << "NumVirtRegs > " << MRI->getNumVirtRegs()
+                      << " threshold, skipping function.\n\n");
+    return false;
+  }
+
   TRI = ST->getRegisterInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
   VRM = &getAnalysis<VirtRegMap>();
@@ -826,9 +841,6 @@
                          AMDGPU::SReg_32RegClass.getNumRegs() / 2 + 1;
   RegsUsed.resize(NumRegBanks);
 
-  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
-               << '\n');
-
   unsigned StallCycles = collectCandidates(MF);
   NumStallsDetected += StallCycles;
 


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