[PATCH] D96517: [AMDGPU] Optimize SGPR to scratch spilling

Thu Feb 25 05:30:17 PST 2021

arsenm added a comment.

In D96517#2587420 <https://reviews.llvm.org/D96517#2587420>, @sebastian-ne wrote:

>> The question is that do we have 30 SGPR spills or we have a spill of SGPR register sequence up to 30 SGPR.
>
> It is 30 separate SGPR spill that happen directly after each other. They are not coalesced currently, but they could be.
>
> The function looks roughly like this:
>
>   100 instructions of saving VGPRs and SGPRs
>   30 real instructions
>   100 instructions of restoring VGPRs and SGPRs
>
> Performance is – as one would expect – not exactly thrilling. There are probably several issues there.

We see the same problem when we have large frame offsets - we end up separately scavenging a register and doing an add for every spill in the sequence to handle the offset. We would probably benefit from adding some kind of spill coalescing before these are lowered

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https://reviews.llvm.org/D96517