[PATCH] D96517: [AMDGPU] Optimize SGPR to scratch spilling

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D96517#2578885 <https://reviews.llvm.org/D96517#2578885>, @hliao wrote:

> In D96517#2574435 <https://reviews.llvm.org/D96517#2574435>, @arsenm wrote:
>
>> I think once we're spilling SGPRs to memory with these tricks, you've given up on performance. We just need *anything* that works, and put effort into guaranteeing we never need to do this (aside from the degenerate inline-asm case using all VGPRs). I'm not worried about getting the ideal SGPR-to-memory sequence
>
> spill doesn't mean we give up performance, specially for large workload, spill is inevitable. the spill performance still matters.

I don't mean general spilling. I mean spilling SGPRs to memory. This is a path that only exists due to a compiler machinery issue, and should not legitimately happen. SGPRs should only spill to VGPRs


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