[PATCH] D97194: [RISCV] Support fixed-length vector sign/zero extension

[Fraser Cormack via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3bc5ed38750c: [RISCV] Support fixed-length vector sign/zero extension (authored by frasercrmck).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97194/new/

https://reviews.llvm.org/D97194

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

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