[PATCH] D97332: [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

It's my understanding that the meaning of `0` could change at some point but I think we can come to that if and when the time comes.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3973
+          .addReg(DestReg, RegState::Define | RegState::Dead)
+          .addReg(MI.getOperand(VLIndex).getReg());
+    }
----------------
This could now be `addReg(VLReg)`?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97332/new/

https://reviews.llvm.org/D97332