[PATCH] D97332: [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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We always create the VL operand using a register, but if we can
determine that it came from an ADDI X0, imm with a sufficiently
small immediate, we can use VSETIVLI.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97332

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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