[PATCH] D97276: [CodeGen] Canonicalise adds/subs of i1 vectors using XOR

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

In D97276#2584555 <https://reviews.llvm.org/D97276#2584555>, @nikic wrote:

> Why is this in getNode() rather than DAGCombine? https://github.com/llvm/llvm-project/commit/6f5a805bbbed5d0cdaaf67846dffa7f044afb407 for example does something very similar in DAGCombine. What's the guideline for correct placement here?

We've followed similar logic as used for i1 based min/max and reductions.  My thinking is that the earlier you can canonicalise expressions the better, and you cannot get earlier than never creating them in the first place.  Ultimately the goal here is that for some operations there is never a need to consider i1 based vectors.  This is partially true today because i1 is rare a legal type.  However i1 vectors are legal for SVE and thus we're hitting corner cases that have not been hit before (for aarch64 at least).


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https://reviews.llvm.org/D97276